The system of claim 1, wherein the first accelerator comprises: a clock receiver configured to receive a first clock signal having the first clock rate a clock generator configured to generate a second clock signal having the second clock rate a gating module coupled to the clock generator and a buffer coupled to the clock receiver, the clock generator, and the gating module, wherein the buffer is configured to store a first packet of the packet stream at the first clock rate and retrieve the stored packet at the second clock rate.ġ1. The system of claim 1, further comprising: a delay unit coupled between the first accelerator and the switch and a packet address decoder coupled between the first accelerator and the switch.ġ0. The system of claim 3, further comprising: a packet splitter coupled to the first accelerator a packet combiner coupled to the first decelerator and an electrical switch coupled between the packet splitter and the packet combiner, wherein the switch is a photonic switch, and wherein the packet splitter is configured to route a first plurality packets of the packet stream having a first plurality of lengths greater than a first threshold to the photonic switch and a second plurality of packets of the packet stream having a second plurality of lengths less than or equal to the first threshold to the electrical switch.ĩ. The system of claim 3, further comprising: a plurality of accelerators coupled to the switch and a plurality of decelerators coupled to the switch.Ĩ. The system of claim 3, further comprising: a first peripheral coupled to the first accelerator and a second peripheral coupled to the first decelerator.ħ. The system of claim 3, further comprising: an electrical-to-optical converter coupled between the first accelerator and the switch and an optical-to-electrical converter coupled between the switch and the first decelerator, wherein the switch is a photonic switch.Ħ.
The system of claim 3, wherein the first clock rate equals the third clock rate.ĥ. The system of claim 1, further comprising a first decelerator coupled to the switch, wherein the first decelerator is configured to re-clock the switched packet stream from the second clock rate to a third clock rate to produce a decelerated packet stream, wherein the second clock rate is greater than the third clock rate, wherein the decelerated packet stream has a third inter-packet gap, and wherein the third inter-packet gap is smaller than the second inter-packet gap.Ĥ. The system of claim 1, further comprising a synchronizer coupled to the first accelerator, wherein the synchronizer is configured to detect the first plurality of leading edges of the plurality of input packets.ģ.
A system for accelerating a packet stream, the system comprising: a first accelerator configured to re-clock a plurality of input packets of the packet stream from a first clock rate to a second clock rate to produce a plurality of accelerated packets of an accelerated packet stream, wherein the first clock rate is less than the second clock rate, wherein a first plurality of leading edges of the plurality of input packets is synchronous with a second plurality of leading edges of the plurality of accelerated packets, wherein the packet stream has a first inter-packet gap, wherein the accelerated packet stream has a second inter-packet gap, and wherein the second inter-packet gap is greater than the first inter-packet gap and a switch coupled to the first accelerator, wherein the switch is configured to switch the accelerated packet stream at the second clock rate to produce a switched packet stream.Ģ.
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